Senior Chip Design Architect: AI-Driven Physical Flow

Ricursive; Palo Alto (CA); On-site; USD 200,000 - 300,000; Full time

Job summary

Ricursive Intelligence is seeking a senior physical design engineer to own the RTL-to-GDSII flow end-to-end, from synthesis to tapeout, in a small, rapidly evolving team.

You will drive timing, power, and signoff for complex blocks at advanced nodes, integrate AI-driven tooling, and build Python/Tcl automation while collaborating with RTL, DFT, and foundry groups. This role shapes how our self-improving design models learn from silicon results.

Qualifications

• BS in EE/CE/CS or closely related field.
• 10+ years of hands-on physical design experience across synthesis to signoff.
• Fluency with production EDA tools and strong Tcl and Python scripting.
• Track record of chip design and tapeout with full signoff closure.
• Proven AI/ML‑driven PPA improvements in physical design.

Responsibilities

• Architect RTL-to-GDSII flow across chip levels, including synthesis, floorplanning, PDN, placement, CTS, routing, and signoff.
• Own timing, power, and physical closure of complex blocks in advanced nodes.
• Deploy and extend AI tooling across the flow for design-space optimization and run orchestration.
• Collaborate with research to train self-improving design models and encode signoff judgement.
• Build Python and Tcl automation for flow orchestration and dashboards.
• Coordinate with RTL, DFT, and foundry teams on design-for-implementability.

Skills

Tcl scripting

Python scripting

EDA tools

AI/ML in PD

Tapeout experience

Education

Bachelor's degree in EE/CE/CS

Master's or PhD in EE/CE/CS

Tools

Synthesis tools

Floorplanning tools

Signoff tools (PrimeTime/Tempus, Calibre)

Job description

Ricursive Intelligence is seeking a senior physical design engineer to own the RTL-to-GDSII flow end-to-end, from synthesis to tapeout, in a small, rapidly evolving team.

You will drive timing, power, and signoff for complex blocks at advanced nodes, integrate AI-driven tooling, and build Python/Tcl automation while collaborating with RTL, DFT, and foundry groups. This role shapes how our self-improving design models learn from silicon results.