Chip Design Flow Architect - RTL to GDSII, EDA

Voltai; United States; On-site; USD 150,000 - 230,000; Full time

Job summary

Voltai seeks a seasoned CAD/EDA engineer to build end-to-end design flows and integrate EDA tools with Voltai's AI systems. You will own RTL-to-GDSII flows and collaborate with ML researchers to generate design data.

The role involves scaling regression and infrastructure, licenses, and on-prem deployments for customers. Strong Python/Tcl and experience with Synopsys/Cadence tools are essential.

Qualifications

• 5+ years of CAD, flow, or methodology experience in semiconductors or EDA.
• Hands-on experience with Synopsys and Cadence tools.
• Strong Python and Tcl, with solid software engineering practices.
• Experience with compute farms like LSF or Slurm.

Responsibilities

• Build and maintain design flows spanning RTL, synthesis, STA, placement, routing, and signoff.
• Integrate commercial EDA tools with Voltai's AI agents and data pipelines.
• Build regression, tracking, and reporting infrastructure for design and verification.
• Manage EDA licenses, compute infrastructure, and job scheduling at scale.
• Partner with ML researchers to generate and curate large-scale design data.
• Support customer deployments in on-prem environments.

Skills

CAD/flow experience

Synopsys tools

Cadence tools

Python

Tcl

LSF/Slurm

RTL-to-GDSII

Tools

Yosys

OpenROAD

Kubernetes

Job description

Voltai seeks a seasoned CAD/EDA engineer to build end-to-end design flows and integrate EDA tools with Voltai's AI systems. You will own RTL-to-GDSII flows and collaborate with ML researchers to generate design data.

The role involves scaling regression and infrastructure, licenses, and on-prem deployments for customers. Strong Python/Tcl and experience with Synopsys/Cadence tools are essential.