Software Engineer, Chip Design

Ricursive Intelligence; Palo Alto (CA); On-site; USD 140,000 - 190,000; Full time

Job summary

Ricrecursive Intelligence is seeking a Software Engineer to build and scale the RTL-to-GDSII flow infrastructure for chip design. You’ll work across the design stack to run complex designs at scale, improving execution, evaluation, and iteration.

Your work will directly impact PPA in production by enabling faster, more reliable design cycles. You will collaborate with domain experts to productize cutting-edge algorithms, automate design analysis, and support production-ready flows across

Qualifications

• Bachelor’s degree in CS, EE, or related field.
• Strong programming skills in Python, C++, Java or similar.
• Working understanding of digital chip design flow from RTL to GDS/physical design.
• Experience integrating or orchestrating EDA tools within engineering workflows.

Responsibilities

• Develop and scale infrastructure behind the end-to-end RTL-to-GDSII flow for scalable design.
• Collaborate with in-house experts to productize cutting-edge algorithms in production flow.
• Build infrastructure to run multi-stage design flows reliably across EDA tools.
• Analyze design metrics like timing violations and routing issues to improve PPA.
• Deploy AI-driven methods to automate design analysis and iteration across the flow.

Skills

Python

C++

Java

AI tooling

Education

Bachelor’s degree in Computer Science, Electrical Engineering, or related technical field

Master’s or PhD in Computer Science, Electrical Engineering, or related technical field

Tools

EDA tools

RTL-to-GDS flow tooling

Job description

Ricrecursive Intelligence is a frontier AI Lab focused on building self-improving systems, starting with chip design. We are reinventing chip development and closing the loop between AI and the hardware that fuels it, recursively accelerating the path to artificial superintelligence.

ABOUT THE ROLE

As a Software Engineer at Ricrecursive, you’ll build the systems and infrastructure that power our end-to-end RTL-to-GDS flow. You’ll work across the broader design stack, improving how we run, evaluate, and iterate on complex chip designs at scale. This includes building reliable execution infrastructure, developing tooling that connects different stages of the flow, improving performance and scalability, and making it easier for our models and engineers to quickly understand the impact of each change. Every improvement compounds: faster runs and tighter feedback loops let us explore more ideas, make better decisions, and reduce iteration cycles. Your work will also have a direct impact on PPA in production. You’ll run against real designs with real constraints, debug issues that only emerge at scale, and make engineering tradeoffs around quality, runtime, robustness, and deadlines—not just performance on academic benchmarks.

WHAT YOU WILL DO

• Develop and scale the infrastructure behind our end-to-end RTL-to-GDSII flow, moving beyond monolithic scripts toward scalable systems that can support hierarchical design, advanced process nodes, and increasingly complex design constraints.
• Work alongside our in-house experts on new ideas to productize cutting-edge algorithms on production flow.
• Build the infrastructure needed to run complex multi-stage design flows reliably across different EDA tools.
• Analyze design metrics like timing violations, congestion, routing issues, and other design problems, helping the overall flow converge faster toward better PPA.
• Deploy AI-driven methods to automate design analysis, optimization, and iteration across the flow.

MINIMUM QUALIFICATIONS

• Bachelor’s degree in Computer Science, Electrical Engineering, or a related technical field.
• Strong programming skills in Python, C++, Java, or a comparable language. Comfortable using modern AI-assisted development tools to navigate complex codebases, debug problems, and accelerate engineering workflows.
• Working understanding of the digital chip design flow, including the major stages from RTL through physical design and signoff.
• Experience integrating, automating, or orchestrating EDA tools as part of larger engineering workflows.
• Demonstrated ability to take ownership of ambiguous technical problems, ramp quickly in unfamiliar areas, and drive work through to production.

PREFERRED QUALIFICATIONS

• Master’s or PhD in Computer Science, Electrical Engineering, or a related technical field.
• Experience with EDA, semiconductor design, distributed systems, or optimization.
• Familiarity with design automation algorithms in one or more areas of the RTL-to-GDS flow, such as placement, timing analysis, RC extraction, netlist processing.
• Demonstrated and quantified the PPA benefit of using AI/ML tooling — AI-driven optimization, ML QoR prediction, or LLM-based flow automation.