Senior Physical Design Flow Architect for AI Inference Chips

The Consensus; San Jose (CA); On-site; USD 170,000 - 250,000; Full time

Benefits offered by this job

Housing subsidy

Relocation support

Daily lunch in office

Wellness benefits

Unlimited compute budget

Job summary

Etched is building a new category of AI hardware in San Jose, focused on frontier inference clusters. As a Physical Design Methodology Engineer, you will own the PD flow from first principles, creating infrastructure that lets design teams iterate rapidly and yield strong PPA gains beyond conventional CAD methods.

You will build automated RTL-to-GDSII flows, manage regression and version control of configurations, and drive dashboards for timing, verification, and utilization while collaborating

Qualifications

• 5-10+ years of PD or PD CAD experience.
• Experience building automated RTL-to-GDSII flows used by multiple block owners.
• Ability to create PG mesh from scratch per design rules and EM/IR analysis.
• Experience with DRC-clean floorplanning flows and automated checks.
• Experience integrating sign-off tools into production flows (PrimeTime, Tempus, Voltus, Pegasus, Calibre).
• Strong Tcl and Python skills for flow development and automation.
• Experience with 5nm nodes or below and UPF-based low power design.

Responsibilities

• Architect, build, and maintain automated RTL-to-GDSII flow from synthesis through signoff.
• Automate PD flows end to end including regression, run management, and configuration control.
• Build and maintain CAD infrastructure, tool qualification, and compute/license efficiency.
• Create dashboards showing timing, physical verification, and utilization trends.
• Drive tool flow optimization and collaborate with EDA vendors on new features.
• Define and audit reference flows, QoR targets, and checklists for third-party PD services.
• Partner with owners to debug flow issues and encode fixes into the methodology.
• Create block-level and full-chip PG mesh and ensure DRC-clean floorplanning.
• Drive PPA tuning and timing correlation from pre-route to signoff.

Skills

PD experience

RTL-to-GDSII flow

Tcl/Python

PPA/timing/convergence

EDA flow automation

Tools

Cadence Innovus

Cadence Genus

Synopsys Fusion Compiler

PrimeTime

Tempus

Voltus

Calibre

Job description

Etched is building a new category of AI hardware in San Jose, focused on frontier inference clusters. As a Physical Design Methodology Engineer, you will own the PD flow from first principles, creating infrastructure that lets design teams iterate rapidly and yield strong PPA gains beyond conventional CAD methods.

You will build automated RTL-to-GDSII flows, manage regression and version control of configurations, and drive dashboards for timing, verification, and utilization while collaborating