Senior Chip Lead, Physical Design & SoC Innovation

Cadence; Austin (TX); On-site; USD 150,000 - 210,000; Full time

Job summary

Cadence is seeking a Senior Physical Design Architect/Chip Lead within the Performance Solutions Group (PSG) to drive RTL-to-GDS services for data centers, AI, and automotive markets. You will lead a team, engage directly with customers, and own technical decisions to meet PPAS targets while selecting optimal foundry/node and libraries.

Experience with 7nm nodes, Cadence tools, and scripting is essential. You will collaborate across RTL/DFT/CAD teams and promote innovative AI-driven

Qualifications

• Fifteen+ years of Physical Design experience.
• Bachelor’s degree in Computer Science/Engineering, Electrical Engineering, or a related field.
• Strong knowledge of Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis.
• Experience with IC digital implementation flows and backend EDA tools including Place & Route, CTA, IR Drop analysis, and power closure.
• Demonstrated experience in complete design closure for chip top-level projects.
• Expertise in PPA optimization to meet aggressive design requirements.
• Experience with advanced nodes at 7nm and below.
• Proficiency in scripting languages such as Tcl, Perl, or Python.
• Strong customer-facing communication and problem-solving skills.
• Experience building technical relationships with RTL, DFT, CAD, and Library teams.

Responsibilities

• Serve as the technical leader for Physical Design and DFT teams, driving complex customer SoC projects from RTL or Netlist to GDS.
• Work directly with customers from initiation to final GDS delivery, owning technical decisions and design trade-offs.
• Guide customers in selecting the appropriate foundry/node, library, and memory compiler, and establish sign-off criteria.
• Collaborate with internal Cadence teams to deliver technical presentations and promote AI initiatives.
• Work closely with RTL/Synthesis teams to ensure key metrics are achieved before the physical design phase gate.
• Partner with Cadence tools R&D to enhance tools and methodologies to meet customer requirements.
• Document and share best practices and lessons learned to improve efficiency and AI adoption.

Skills

Digital Design

PPA optimization

Scripting Tcl/Perl/Python

Customer-facing communication

Education

Bachelor’s degree in CS/Engineering or Electrical Engineering

Master’s degree (preferred)

Tools

Cadence Genus

Cadence Innovus

Conformal

Tempus

Modus

Voltus

ICC/ICC2

PrimeTime

Job description

Cadence is seeking a Senior Physical Design Architect/Chip Lead within the Performance Solutions Group (PSG) to drive RTL-to-GDS services for data centers, AI, and automotive markets. You will lead a team, engage directly with customers, and own technical decisions to meet PPAS targets while selecting optimal foundry/node and libraries.

Experience with 7nm nodes, Cadence tools, and scripting is essential. You will collaborate across RTL/DFT/CAD teams and promote innovative AI-driven