Senior ASIC Verification Engineer — Pre-Silicon, Emulation & Formal

Jobs Paloaltonetworks; California; On-site; USD 129,000 - 209,000; Full time

Job summary

Palo Alto Networks in California seeks a Design Verification engineer for the ASIC team to ensure next-generation firewall devices meet high standards of features, performance, and reliability.

You will define verification methodologies, architect test benches, write tests, and debug across simulation, emulation, formal verification, and silicon validation. Office-based with four days in the office per week.

Qualifications

• BS in EE, CE, or CS required or equivalent military experience required
• Minimum 5 years experience in ASIC design verification
• Demonstrated success in taking multiple ASIC products from concept to mass production
• Expertise in SystemVerilog and UVM

Responsibilities

• Collaborate with engineers in software, architecture, design, and verification teams to create comprehensive pre-silicon verification plans across simulation, emulation, and formal verification
• Plan and execute every aspect of simulation test plans using coverage-driven, constrained-random methodologies
• Develop flows, methodologies, and infrastructure for emulation and debugging
• Define new tools and methodologies to improve quality and velocity
• Create Python programs to automate triage, coverage closure, and metrics-driven verification

Skills

SystemVerilog/UVM

Education

BS in EE, CE, or CS

Tools

SystemVerilog/UVM

Job description

Palo Alto Networks in California seeks a Design Verification engineer for the ASIC team to ensure next-generation firewall devices meet high standards of features, performance, and reliability.

You will define verification methodologies, architect test benches, write tests, and debug across simulation, emulation, formal verification, and silicon validation. Office-based with four days in the office per week.