Senior ASIC Verification Engineer — Data Center Innovation

Anysilicon; San Jose (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

Cisco is seeking an ASIC Design Verification Engineer in Silicon Valley to advance verification for high-performance ASICs powering core switching, routing, and wireless products. The role involves defining architectures, developing verification environments, and leading DV efforts.

The candidate will build DV environments, implement coverage, and run simulations across ASIC and system levels, collaborating on post-silicon validation and lab bring-up.

Qualifications

• Bachelor's degree in Computer, Electrical, or Electronics Engineering with 7+ years of relevant experience, or a Master's with 4+ years.
• Experience in SystemVerilog or UVM methodologies and object-oriented programming concepts.
• Experience leading verification teams or managing project assignments.

Responsibilities

• Define, architecture, and design high-performance ASICs with ownership of complex areas.
• Define verification methodologies and reusable code for future projects.
• Lead DV efforts and resolve block-level to chip-level issues.

Skills

SystemVerilog

UVM

OOP concepts

Python scripting

Perl scripting

PCIe knowledge

Education

Bachelor's degree in Computer, Electrical, or Electronics Engineering

Master's degree in a relevant field

Tools

Veloce

Palladium

Zebu

HAPS

Job description

Cisco is seeking an ASIC Design Verification Engineer in Silicon Valley to advance verification for high-performance ASICs powering core switching, routing, and wireless products. The role involves defining architectures, developing verification environments, and leading DV efforts.

The candidate will build DV environments, implement coverage, and run simulations across ASIC and system levels, collaborating on post-silicon validation and lab bring-up.