Senior ASIC Verification Engineer - Data Center DV

Cisco Systems, Inc; San Jose (CA); On-site; USD 155,000 - 223,000; Full time

Benefits offered by this job

Medical/dental/vision

401(k) with company matching

Paid parental leave

Paid time off

Job summary

Cisco Systems, Inc. is seeking an ASIC Design Verification Engineer in San Jose, CA, onsite. The role focuses on architecting and expanding DV infrastructure, building scalable test benches, and developing comprehensive test plans for complex silicon.

You will collaborate across design, architecture, and software teams to ensure robust verification, post-silicon bring-up, and integration, with opportunities to work in emulation environments and with state‑of‑the‑art silicon platforms.

Qualifications

• Experience with SystemVerilog or UVM methodologies.
• Experience building reusable, scalable test benches from scratch.
• Scripting experience with Perl and/or Python.

Responsibilities

• Architect, develop, and maintain DV infrastructure for block, cluster, and top-level environments.
• Build DV environments from scratch for block and cluster levels.
• Develop, implement, and enhance test plans and tests for block and cluster verification with constraint-random and directed stimulus.
• Ensure coverage through code and functional coverage implementation and review.
• Qualify RTL designs by running gate-level simulations on netlists.
• Collaborate with designers, architects, and software teams to debug post-silicon bring-up issues.
• Support design testing in emulation environments.

Skills

SystemVerilog/UVM

Test bench design

Python/Perl scripting

Education

Bachelor’s degree in Electrical/Computer Engineering

Master’s degree in a related field

Tools

Veloce

Palladium

Zebu

HAPS

Job description

Cisco Systems, Inc. is seeking an ASIC Design Verification Engineer in San Jose, CA, onsite. The role focuses on architecting and expanding DV infrastructure, building scalable test benches, and developing comprehensive test plans for complex silicon.

You will collaborate across design, architecture, and software teams to ensure robust verification, post-silicon bring-up, and integration, with opportunities to work in emulation environments and with state‑of‑the‑art silicon platforms.