Junior ASIC Verification Engineer (SV/UVM)

Cisco Systems, Inc.; San Jose (CA); Vor Ort; USD 100.000 - 165.000; Vollzeit

Zusammenfassung

Cisco Systems, Inc. is seeking an ASIC Engineer to advance verification of our data center silicon.

You will collaborate with verification engineers, designers, and hardware teams to verify ASICs in simulation and emulation, and assist bring-up for seamless integration. The role focuses on maintaining DV environments, building test benches from scratch, and driving verification closure with strong SystemVerilog/UVM skills.

Qualifikationen

• A Bachelor's degree in ASIC Design, Design Verification, or a related field.
• Qualifying education and work experience should be in ASIC Design, Design Verification, or a related field.
• Qualifying education and work experience should be in ASIC Engineering, Verification or a related field.
• Experience with SystemVerilog and UVM methodology.
• Experience with scripting using Perl and/or Python.

Aufgaben

• Maintaining existing DV environments and enhancing them.
• Construct test bench including scoreboard, agents, sequencers, and monitors for new blocks.
• Write test plan, develop test cases, debug regression failures and drive to module verification closure.
• Ensuring complete verification coverage through implementation and review of code and functional coverage.

Kenntnisse

SystemVerilog

UVM

Perl

Python

Ausbildung

Bachelor's degree in ASIC Design / Design Verification or related field

Tools

Veloce/HAPS

Jobbeschreibung

Cisco Systems, Inc. is seeking an ASIC Engineer to advance verification of our data center silicon.

You will collaborate with verification engineers, designers, and hardware teams to verify ASICs in simulation and emulation, and assist bring-up for seamless integration. The role focuses on maintaining DV environments, building test benches from scratch, and driving verification closure with strong SystemVerilog/UVM skills.