Senior ASIC Verification Engineer — UVM, SoC & Coverage

Enormous Enterprise LLC; Sunnyvale (CA); Hybrid; USD 140,000 - 180,000; Full time

Job summary

Enormous Enterprise LLC in Sunnyvale, CA is seeking a highly capable ASIC Verification Engineer to join our networking silicon development team. This hybrid role requires you to be in the office two days per week.

You will own block- or subsystem-level verification, develop robust UVM environments, and drive coverage closure across test plans. The role demands strong SystemVerilog, UVM, and waveform debugging skills to ensure high-quality ASIC/SoC deliverables.

Qualifications

• 5+ years of ASIC/SoC verification with ownership from test plan to coverage closure.
• Strong SystemVerilog and UVM expertise, building environments from scratch.
• Experience with test planning, coverage analysis, and debugging complex SoC designs.
• Proficiency with Cadence Xcelium, Synopsys VCS, Mentor Questa and waveform debugging.

Responsibilities

• Own block- or subsystem-level verification with test plans and coverage closure.
• Develop and maintain advanced UVM environments with agents, sequences, scoreboards.
• Perform constrained random testing and debug to achieve coverage goals.
• Analyze simulations using Cadence Xcelium, VCS, Questa and debug waveforms.
• Collaborate with cross-functional teams to deliver quality ASIC/SoC.

Skills

SystemVerilog & UVM

Constrained randomization

Functional coverage

SVA assertions

Test planning

Debugging SoC designs

Simulation workflow

Tools

Cadence Xcelium

Synopsys VCS

Mentor Questa

UVM environments

Job description

Enormous Enterprise LLC in Sunnyvale, CA is seeking a highly capable ASIC Verification Engineer to join our networking silicon development team. This hybrid role requires you to be in the office two days per week.

You will own block- or subsystem-level verification, develop robust UVM environments, and drive coverage closure across test plans. The role demands strong SystemVerilog, UVM, and waveform debugging skills to ensure high-quality ASIC/SoC deliverables.