Senior ASIC Verification Engineer (Hybrid) — Lead & Mentor

Hewlett Packard Enterprise Development LP; BLOOMINGTON, Northern (MN, KY); Hybrid; USD 135,000 - 311,000; Full time

Benefits offered by this job

Health & Wellbeing

Career development

Inclusive culture

Job summary

Hewlett Packard Enterprise seeks a Senior ASIC Design Verification Engineer to lead pre-silicon verification for Slingshot NIC/switch blocks. The role emphasizes ownership of verification scope, development of SystemVerilog/UVM testbenches, and driving coverage and bug closure alongside seasoned architects in a hybrid office setting.

The position requires 10+ years in VLSI design/verification, deep SystemVerilog/UVM expertise, and strong scripting skills.

Qualifications

• 10+ years of experience in VLSI design, verification, or implementation.
• Expert level knowledge of SystemVerilog and of UVM methodologies (OVM acceptable).
• Expert level programming/scripting skills and knowledge of HDL, EDA, and FPGA tools.

Responsibilities

• Define and follow the team's design verification methodology.
• Develop SystemVerilog and UVM testbenches; create bus functional models to drive/stimulus.
• Plan and implement block/integration level scoreboards and checkers.
• Write and analyze functional coverage; contribute to milestones.
• Triage regression failures; drive bug closure.
• Apply scripting, automation, and AI-assisted tools to speed verification.
• Mentor less experienced staff and influence verification strategy.
• Drive innovation by integrating new technologies in design projects.

Skills

SystemVerilog

UVM/OVM

Python

Perl

Tcl

EDA tools

FPGA tools

English communication

Problem solving

Education

Bachelor's or Master's in EE/CE/CS

Tools

EDA tools

FPGA tools

Job description

Hewlett Packard Enterprise seeks a Senior ASIC Design Verification Engineer to lead pre-silicon verification for Slingshot NIC/switch blocks. The role emphasizes ownership of verification scope, development of SystemVerilog/UVM testbenches, and driving coverage and bug closure alongside seasoned architects in a hybrid office setting.

The position requires 10+ years in VLSI design/verification, deep SystemVerilog/UVM expertise, and strong scripting skills.