Senior ASIC Verification Engineer – Hybrid (Sunnyvale)

HITEC; Sunnyvale (CA); Hybrid; USD 159,000 - 321,000; Full time

Benefits offered by this job

Health benefits

Hybrid work arrangement

Inclusive culture

Job summary

Hewlett Packard Enterprise seeks a highly skilled Senior ASIC Verification Engineer to join our networking silicon team in Sunnyvale, CA. The role focuses on building high-speed ASIC verifications, from tests to coverage closure, using SystemVerilog/UVM and industry tools.

You will work in a hybrid onsite setting, collaborating across engineering and test groups, and contribute to complex SoC designs with extensive debug and regression efforts.

Qualifications

• 10+ years of ASIC/SoC verification experience from test plan to coverage closure.
• Strong SystemVerilog and UVM expertise.
• Experience with industry-standard simulators and waveform debugging.
• Constraint-driven random testing and assertion goals (SVA).

Responsibilities

• Own and drive block-level or subsystem verification efforts from test plans to coverage closure.
• Develop, enhance, and maintain advanced UVM verification environments (agents, sequences, scoreboards).
• Perform constraint-driven random testing and debug complex SoC designs.
• Collaborate with cross-functional teams to ensure high-quality ASIC/SoC deliverables.

Skills

SystemVerilog

UVM

SoC verification

Test planning

Coverage analysis

Debugging

Collaboration

Randomization

Assertions (SVA)

Waveform debugging

Tools

Cadence Xcelium

Synopsys VCS

Mentor Questa

Job description

Hewlett Packard Enterprise seeks a highly skilled Senior ASIC Verification Engineer to join our networking silicon team in Sunnyvale, CA. The role focuses on building high-speed ASIC verifications, from tests to coverage closure, using SystemVerilog/UVM and industry tools.

You will work in a hybrid onsite setting, collaborating across engineering and test groups, and contribute to complex SoC designs with extensive debug and regression efforts.