Principal ASIC Design Engineer | Hybrid, Equity & Bonus

HP Enterprise; Sunnyvale (CA); Hybrid; USD 180,000 - 290,000; Full time

Benefits offered by this job

Annual equity awards

Hybrid work model

Annual bonus

Job summary

HP Enterprise in Sunnyvale, CA is seeking an experienced VLSI/ASIC architect to design and verify complex networking chip subsystems. You will write both functional and micro-architecture specifications, implement in Verilog/SystemVerilog, and drive timing and power optimizations.

You will collaborate with verification and physical design teams, lead major modules, and mentor junior engineers while maintaining high standards in performance and efficiency.

Qualifications

• Bachelor’s degree in Electrical Engineering required.
• Master’s degree strongly desired.
• 15+ years of relevant experience.
• Strong knowledge of synthesis, lint and ASIC development tools.
• Knowledge of Computer Architecture and networking protocols is highly desired.
• Excellent written and verbal communications skills.

Responsibilities

• Architect complex modules and subsystems for high performance networking chips.
• Write functional and micro-architecture specs and implement in Verilog/SystemVerilog.
• Collaborate with verification and physical design teams to meet timing and power targets.
• Lead or mentor junior engineers and interns and contribute to knowledge sharing.

Skills

Analytical thinking/problem solving

Communication skills

Leadership/mentorship

Education

BSEE (MSEE preferred)

Tools

Verilog/SystemVerilog

Synthesis/Lint tools

Perl

Python

Job description

HP Enterprise in Sunnyvale, CA is seeking an experienced VLSI/ASIC architect to design and verify complex networking chip subsystems. You will write both functional and micro-architecture specifications, implement in Verilog/SystemVerilog, and drive timing and power optimizations.

You will collaborate with verification and physical design teams, lead major modules, and mentor junior engineers while maintaining high standards in performance and efficiency.