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Hewlett Packard Enterprise in Colorado is seeking a Senior ASIC Design Verification Engineer to lead pre-silicon verification across multiple projects. The role emphasizes SystemVerilog, UVM/OVM, and strong scripting skills to accelerate verification and coverage closure in a hybrid work model.
You will mentor staff, drive innovation, and contribute to the selection of future technical leaders while collaborating in a distributed team environment.
Hewlett Packard Enterprise in Colorado is seeking a Senior ASIC Design Verification Engineer to lead pre-silicon verification across multiple projects. The role emphasizes SystemVerilog, UVM/OVM, and strong scripting skills to accelerate verification and coverage closure in a hybrid work model.
You will mentor staff, drive innovation, and contribute to the selection of future technical leaders while collaborating in a distributed team environment.