Senior ASIC Design & Verification Engineer - Hybrid Sunnyvale

Salt; San Francisco (CA); Hybrid; USD 140,000 - 200,000; Full time

Job summary

Salt in Sunnyvale, CA seeks an experienced ASIC Design and/or Verification Engineer (Sr. to Principal) for a hybrid role. You will architect and verify modules for high-performance networking chips, write detailed specs, and implement RTL using Verilog/SystemVerilog.

Collaborate with the physical design team for timing closure, create coverage with SVA, and mentor junior engineers to ensure full block validation and robust netlists.

Qualifications

• Experience leading high-performance subsystems from specification to final netlist.
• Proficient in Verilog/SystemVerilog coding.
• Knowledge of computer architecture and networking protocols.
• Strong written and verbal communication skills.
• Proficiency in Perl/Python.

Responsibilities

• Architect/verify complex modules and subsystems used in high performance networking chips.
• Write detailed functional and micro-architecture specifications for your module.
• Implement the design/verification using Verilog or System Verilog.
• Write functional coverage/SVA to help verification catch corner case bugs.
• Collaborate with Physical Design team for timing closure and fix RTL timing as needed.
• Work with Design/Verification teams to ensure full validation of your block.
• Show leadership and provide guidance to new engineers and interns.

Skills

Verilog/SystemVerilog

Leadership

Computer architecture

Networking protocols

Perl/Python

Education

Bachelor’s degree in Engineering

Master’s degree strongly desired

Tools

Synthesis tools

Lint tools

ASIC development tools

Job description

Salt in Sunnyvale, CA seeks an experienced ASIC Design and/or Verification Engineer (Sr. to Principal) for a hybrid role. You will architect and verify modules for high-performance networking chips, write detailed specs, and implement RTL using Verilog/SystemVerilog.

Collaborate with the physical design team for timing closure, create coverage with SVA, and mentor junior engineers to ensure full block validation and robust netlists.