Senior ASIC Verification Architect — Hybrid (2 days in office)

HITEC; Chippewa Falls (WI); Hybrid; USD 140,000 - 321,000; Full time

Benefits offered by this job

Hybrid work model

Inclusive culture

Job summary

Hewlett Packard Enterprise is seeking a Senior ASIC Design Verification Engineer to lead pre-silicon verification across projects. You will develop SystemVerilog/UVM testbenches, create scoreboards, drive coverage, and mentor junior staff within a hybrid US-based team.

The role emphasizes strong programming and scripting skills, expert problem solving, and collaboration in a distributed environment. A Bachelor’s or Master’s in EE/CE/CS and 10+ years of VLSI experience are required.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent.
• 10+ years of experience in VLSI design, verification, or implementation.

Responsibilities

• Define verification methodology and test-plan
• Develop SystemVerilog testbenches and UVM components
• Plan and implement block/integration scoreboards and checkers
• Write/analyze functional coverage and sign-off reviews
• Triage regression failures and drive bug closure
• Apply scripting, automation, and AI-assisted tools to verification
• Provide guidance and mentoring to staff
• Drive integration of new technologies in design projects

Skills

SystemVerilog

UVM/OVM

English communication

Problem solving

Education

Bachelor's or Master's in EE/CE/CS

Tools

EDA tools

FPGA tools

Job description

Hewlett Packard Enterprise is seeking a Senior ASIC Design Verification Engineer to lead pre-silicon verification across projects. You will develop SystemVerilog/UVM testbenches, create scoreboards, drive coverage, and mentor junior staff within a hybrid US-based team.

The role emphasizes strong programming and scripting skills, expert problem solving, and collaboration in a distributed environment. A Bachelor’s or Master’s in EE/CE/CS and 10+ years of VLSI experience are required.