Senior ASIC Verification Engineer – Hybrid, HPC NICs

Hewlett Packard Enterprise; Chippewa Falls (WI); Hybrid; USD 140,000 - 321,000; Full time

Job summary

Hewlett Packard Enterprise seeks a Senior Design Verification Engineer to lead pre-silicon verification for Slingshot NIC/ASICs. You will define verification scope, drive testbench components, and mentor a distributed team of engineers in SystemVerilog, UVM techniques, and AI-assisted workflows.

The role emphasizes high‑performance interconnects for HPC/AI, with opportunities to shape verification methodology and adopt agentic AI tools across projects.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent.
• 10+ years of experience in VLSI design, verification, or implementation.

Responsibilities

• Follow and help define the team's design verification methodology.

Skills

SystemVerilog

UVM

Scripting

English proficiency

VLSI design verification

Block/systems verification

Education

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent

Tools

SystemVerilog

OVM/UVM

EDA tools

FPGA tools

Job description

Hewlett Packard Enterprise seeks a Senior Design Verification Engineer to lead pre-silicon verification for Slingshot NIC/ASICs. You will define verification scope, drive testbench components, and mentor a distributed team of engineers in SystemVerilog, UVM techniques, and AI-assisted workflows.

The role emphasizes high‑performance interconnects for HPC/AI, with opportunities to shape verification methodology and adopt agentic AI tools across projects.