Hybrid Senior ASIC Verification Architect

Hewlett Packard Enterprise; Sunnyvale (CA); Hybrid; USD 181,000 - 367,000; Full time

Job summary

Hewlett Packard Enterprise in Sunnyvale, CA, is seeking a Senior ASIC Verification Engineer to lead block- and subsystem-verification efforts within a fast-paced silicon group. You will craft test plans, build and maintain UVM environments, and drive coverage to closure in a collaborative setting.

Responsibilities include constraint-driven random testing, debugging complex SoCs, and using Cadence Xcelium, Synopsys VCS, and Mentor Questa to validate designs.

Qualifications

• 15+ years of experience in ASIC/SoC verification with ownership from test plan to coverage closure.
• Strong SystemVerilog and UVM expertise, able to build environments from scratch.
• Deep knowledge of randomization, constraints, functional coverage, and assertions (SVA).
• Hands-on test planning, coverage analysis, and debugging of complex SoC designs.

Responsibilities

• Own and drive block-level or subsystem verification efforts, from creating test plans to achieving comprehensive coverage closure.
• Develop, enhance, and maintain advanced UVM verification environments, including agents, sequences, scoreboards, virtual sequences, and register models.
• Perform constraint-driven random testing, debug complex SoC designs, and ensure functional coverage and assertion goals are met.
• Analyze simulation results using industry-leading simulation tools and debug waveforms to validate design functionality.
• Collaborate with cross-functional teams to identify and resolve issues, ensuring high-quality ASIC/SoC deliverables.

Skills

SystemVerilog

UVM

Test planning

Coverage analysis

Debugging

SoC verification

Randomization

SVA

Tools

Cadence Xcelium

Synopsys VCS

Mentor Questa

Job description

Hewlett Packard Enterprise in Sunnyvale, CA, is seeking a Senior ASIC Verification Engineer to lead block- and subsystem-verification efforts within a fast-paced silicon group. You will craft test plans, build and maintain UVM environments, and drive coverage to closure in a collaborative setting.

Responsibilities include constraint-driven random testing, debugging complex SoCs, and using Cadence Xcelium, Synopsys VCS, and Mentor Questa to validate designs.