Lead ASIC Verification Engineer (SoC/Networking)

Hewlett Packard Enterprise Development LP; Durham (NC); On-site; USD 120,000 - 180,000; Full time

Job summary

Hewlett Packard Enterprise Development LP seeks an experienced ASIC/SoC verification engineer to lead verification efforts for complex networking SoCs. You will own test plans, develop environments from scratch, and drive coverage closure across block, subsystem, and full-chip levels.

The role requires hands-on expertise in SystemVerilog, UVM, and modern verification methodologies, with exposure to emulation and post-silicon bring-up advantages.

Qualifications

• 4+ years in ASIC/SoC verification with test-plan ownership.
• Strong SystemVerilog and UVM experience.
• Understanding of randomization, constraints, functional coverage, and SVA.
• Hands-on test planning, coverage analysis, and debugging of complex SoCs.
• Familiar with coverage analytics, regression dashboards, and CI flows.
• Knowledge of low-power UPF or formal verification is a plus.
• Exposure to emulation environments and hardware acceleration is desirable.
• Experience with post-silicon bring-up and debug is beneficial.

Responsibilities

• Own and drive block-level to FullChip verification efforts from test plans to coverage closure.
• Develop verification environments from scratch and maintain test benches.
• Plan, execute, and optimize verification strategies for networking ASICs.
• Leverage simulation, emulation, and waveform debugging to verify design intent.
• Contribute to regression suites and CI integration for ongoing QA.

Skills

ASIC/SoC verification

SystemVerilog

UVM methodology

test planning

coverage analysis

debugging

emulation environments

waveform debugging

post-silicon bring-up

CI/regression dashboards

Tools

Cadence Xcelium

Synopsys VCS

Mentor Questa

Job description

Hewlett Packard Enterprise Development LP seeks an experienced ASIC/SoC verification engineer to lead verification efforts for complex networking SoCs. You will own test plans, develop environments from scratch, and drive coverage closure across block, subsystem, and full-chip levels.

The role requires hands-on expertise in SystemVerilog, UVM, and modern verification methodologies, with exposure to emulation and post-silicon bring-up advantages.