Senior ASIC Verification Engineer - Hybrid (HPC/NIC)

Hewlett Packard Enterprise; Fort Collins (CO); Hybrid; USD 142,000 - 270,000; Full time

Job summary

Hewlett Packard Enterprise seeks a Senior Design Verification Engineer for our hybrid role with ~2 days in-office per week in Colorado. You will drive verification for Slingshot ASICs, mentor engineers, and shape verification methodology in a distributed team.

Lead SystemVerilog/UVM components, develop testbenches, plan scoreboards, and guide bug closure while leveraging AI-assisted tooling to accelerate verification for HPC/AI applications.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent.
• 10+ years of experience in VLSI design, verification, or implementation.

Responsibilities

• Follow and help define the team's design verification methodology.
• Develop SystemVerilog and UVM testbench components, including bus functional models that drive and monitor stimulus.
• Plan and implement block and integration level scoreboards and checkers to verify functional behavior.
• Write and analyze functional coverage, providing input to block level milestones.
• Triage regression failures and identify logic bugs, while driving bug closure.
• Apply scripting, automation, and AI-assisted and agentic tools to improve the speed and quality of the verification process.
• Provide guidance and mentoring to less experienced staff members to set an example of VLSI design and development innovation and excellence.

Skills

SystemVerilog

UVM/OVM

Scripting (Python)

HDL/EDA tools

English communication

Distributed teamwork

Education

Bachelor's or Master's in Electrical/Computer Engineering or CS

Tools

FPGA tools

Linux scripting

HDL design tools

Job description

Hewlett Packard Enterprise seeks a Senior Design Verification Engineer for our hybrid role with ~2 days in-office per week in Colorado. You will drive verification for Slingshot ASICs, mentor engineers, and shape verification methodology in a distributed team.

Lead SystemVerilog/UVM components, develop testbenches, plan scoreboards, and guide bug closure while leveraging AI-assisted tooling to accelerate verification for HPC/AI applications.