Senior Verification Design Engineer: High-Speed IP & PHY

Synopsys, Inc.; Boxborough (MA); On-site; USD 150,000 - 230,000; Full time

Job summary

Synopsys, Inc. seeks an experienced design verification engineer to verify complex digital IP and interfaces.

You will develop verification strategies for PHY, DDRIO, UCIe and other high-speed IP, and architect SystemVerilog/UVM testbenches and verification environments. You will drive constrained-random tests, assertions, functional coverage and coverage models, and ensure verification closure through debugging and signoff.

Qualifications

• 12+ years of relevant experience in ASIC/IP verification or equivalent
• Proven track record delivering verification closure for complex IP
• Strong SystemVerilog and UVM expertise with testbench development and coverage
• Experience with PHY, DDR/UCIe, SERDES, PCIe or similar high-speed interfaces

Responsibilities

• Develop verification strategies for PHY, DDRIO, UCIe and other high-speed IP
• Architect SystemVerilog/UVM testbenches and reusable verification environments
• Create directed and constrained-random tests, assertions and coverage models
• Drive coverage and signoff through regression analysis and debugging
• Collaborate with RTL, architecture, firmware and modeling teams
• Mentor engineers and advance verification methodologies

Skills

SystemVerilog

UVM

debug

high-speed verification

verification strategies

Education

BS in Electrical Engineering

MS in Electrical Engineering

Tools

Simulation tools

Job description

Synopsys, Inc. seeks an experienced design verification engineer to verify complex digital IP and interfaces.

You will develop verification strategies for PHY, DDRIO, UCIe and other high-speed IP, and architect SystemVerilog/UVM testbenches and verification environments. You will drive constrained-random tests, assertions, functional coverage and coverage models, and ensure verification closure through debugging and signoff.