Senior ASIC Verification Architect

Cisco Systems, Inc.; San Jose (CA); Presencial; USD 168.000 - 245.000; Jornada completa

Descripción de la vacante

Cisco Systems, Inc. is hiring an experienced ASIC verification engineer for the Silicon One team in San Jose. You will participate in design verification of Cisco’s high-end switching products and architect DV environments to support multi-chip and full-chip verification.

You will develop testbenches, models, and coverage, collaborating with designers and software teams to debug issues during bring-up and ensure robust verification across complex SoC architectures.

Formación

• Bachelor's degree with 7+ years of related experience, or Master's with 4+ years, or PhD with 1 year.
• Strong experience in System Verilog and UVM.
• Experience with ASIC design and verification processes, debugging, methodology, and tools.
• Experience in verifying blocks/clusters or full chip level for ASIC.

Responsabilidades

• Participate in ASIC design verification for Cisco high-end switching products.
• Architect, develop, and maintain DV environment infrastructure.
• Develop simulation models, test plans, random tests, and coverage.
• Construct testbenches components like scoreboard, agents, sequencers, and monitors.
• Collaborate with designers, architects, and software teams during post-silicon bring-up.
• Ensure comprehensive verification coverage through code and functional coverage.

Conocimientos

C/C++

Python

Networking fundamentals

Troubleshooting

Educación

Bachelor's degree in electrical/computer engineering or related field

Master's degree in electrical/computer engineering or related field

PhD in electrical/computer science/engineering

Herramientas

SystemVerilog

UVM

Verilog

Linux

PCIe

AXI protocols

Descripción del empleo

Cisco Systems, Inc. is hiring an experienced ASIC verification engineer for the Silicon One team in San Jose. You will participate in design verification of Cisco’s high-end switching products and architect DV environments to support multi-chip and full-chip verification.

You will develop testbenches, models, and coverage, collaborating with designers and software teams to debug issues during bring-up and ensure robust verification across complex SoC architectures.