Senior ASIC Architect & Technical Leader

020 Cisco Systems, Inc.; San Jose (CA); Sur place; USD 187 000 - 268 000; Plein temps

Résumé du poste

The Silicon One team at Cisco Systems, Inc. seeks an experienced ASIC design professional to drive high-quality structural and functional tests, diagnostic features, and IP development.

You will collaborate with Front-end RTL and backend physical design teams to ensure robust silicon solutions meeting Cisco's standards. Candidates should have a strong background in Verilog/SystemVerilog, CDC/RDC, and front-end toolchains, plus experience with AMBA protocols and JTAG.

Qualifications

• Bachelor's or Master's in Electrical or Computer Engineering with 10+ years in ASIC digital design.
• Proficient in Verilog/SystemVerilog coding.
• Experience with CDC/RDC concepts and design implementation.
• Experience with front-end tools: Verilog simulators, linting, CDC checkers, synthesis, formal verification.
• Experience with AMBA (AXI, APB, AHB), memories, and JTAG interfaces.

Responsabilités

• Drive structural and functional tests, as well as diagnostic feature implementation and IP development/integration.
• Develop test access methods and ensure high-speed IO protocols meet Cisco’s standards.
• Collaborate with Front-end RTL and backend physical design teams to understand chip architecture and improve verification coverage.
• Ensure silicon solutions are robust and scalable within Cisco Silicon One architecture.

Connaissances

Verilog/SystemVerilog

CDC/RDC concepts

AMBA interfaces (AXI/APB/AHB)

Synthesis & formal verification

Formation

Bachelor's or Master's Degree in Electrical or Computer Engineering

Outils

Verilog simulators

linting

CDC checkers

synthesis tools

formal verification

JTAG

memories interfaces

Description du poste

The Silicon One team at Cisco Systems, Inc. seeks an experienced ASIC design professional to drive high-quality structural and functional tests, diagnostic features, and IP development.

You will collaborate with Front-end RTL and backend physical design teams to ensure robust silicon solutions meeting Cisco's standards. Candidates should have a strong background in Verilog/SystemVerilog, CDC/RDC, and front-end toolchains, plus experience with AMBA protocols and JTAG.