ASIC Design Verification Engineer I [Full Time] – United States

AnySilicon; San Jose (CA); On-site; USD 120,000 - 160,000; Full time

Job summary

Cisco's Silicon One team is seeking an ASIC Design Verification Engineer I for the United States. The role focuses on verifying ASIC designs and building robust DV environments to support Cisco's core networking platforms.

The ideal candidate brings SystemVerilog and UVM expertise, scripting skills in Perl or Python, and experience delivering constrained-random DV environments. You will collaborate across teams to ensure high-quality verification coverage.

Qualifications

• Bachelor's degree in ASIC Design, Design Verification or related field.
• Experience in ASIC Engineering or Verification is required.
• Proficient in SystemVerilog and UVM.
• Experience with coverage-driven verification and DV environments.
• Ability to build test benches from scratch and implement SystemVerilog constraints, classes and structures.

Responsibilities

• Collaborate with verification engineers, designers, and cross-functional teams to ensure seamless integration of ASICs.
• Maintain and enhance existing design verification environments.
• Construct test benches including scoreboards, agents, sequencers, and monitors for new blocks.
• Write test plans, develop test cases, debug regression failures, and drive module verification closure.
• Ensure complete verification coverage through code and functional coverage implementation and review.

Skills

SystemVerilog

UVM

Perl

Python

Constrained random

Test benches

Test plans

Communication

Education

Bachelor's degree in ASIC Design or related field

Job description

ASIC Design Verification Engineer I [Full Time] – United States

Cisco is seeking potential candidates for future ASIC Engineer roles within the Silicon One team, which focuses on innovative hardware platforms essential for the AI era. This team is responsible for powering Cisco’s core Switching, Routing, and Wireless products globally, emphasizing creativity and collaboration in product development.

Responsibilities:

• Collaborate with verification engineers, designers, and cross-functional teams to ensure seamless integration of ASICs.
• Maintain and enhance existing design verification (DV) environments.
• Construct test benches including scoreboards, agents, sequencers, and monitors for new blocks.
• Write test plans, develop test cases, debug regression failures, and drive module verification closure.
• Ensure complete verification coverage through code and functional coverage implementation and review.

Qualifications:

• Bachelor's degree in ASIC Design, Design Verification, or a related field, completed within the past 3 years or expected within the next 12 months.
• Experience in ASIC Engineering or Verification.

Skills:

• Proficiency in System Verilog and UVM methodology.
• Scripting experience using Perl and/or Python.
• Experience with functional coverage and constrained random DV environments.
• Ability to build test benches from scratch, including knowledge of System Verilog constraints, structures, and classes.
• Effective verbal and written communication skills.

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

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• ASIC Design Services
• Verification
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