Senior ASIC Design Verification Engineer

Anysilicon; San Jose (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

Cisco is seeking an ASIC Design Verification Engineer in Silicon Valley to advance verification for high-performance ASICs powering core switching, routing, and wireless products. The role involves defining architectures, developing verification environments, and leading DV efforts.

The candidate will build DV environments, implement coverage, and run simulations across ASIC and system levels, collaborating on post-silicon validation and lab bring-up.

Qualifications

• Bachelor's degree in Computer, Electrical, or Electronics Engineering with 7+ years of relevant experience, or a Master's with 4+ years.
• Experience in SystemVerilog or UVM methodologies and object-oriented programming concepts.
• Experience leading verification teams or managing project assignments.

Responsibilities

• Define, architecture, and design high-performance ASICs with ownership of complex areas.
• Define verification methodologies and reusable code for future projects.
• Lead DV efforts and resolve block-level to chip-level issues.

Skills

SystemVerilog

UVM

OOP concepts

Python scripting

Perl scripting

PCIe knowledge

Education

Bachelor's degree in Computer, Electrical, or Electronics Engineering

Master's degree in a relevant field

Tools

Veloce

Palladium

Zebu

HAPS

Job description

Join the Silicon One team at Cisco as an ASIC Design Verification Engineer, where you'll contribute to innovative hardware platforms that power core Switching, Routing, and Wireless products globally. This role is pivotal in shaping the future of technology through the development of cutting-edge data center solutions.

Responsibilities:

• Drive the definition, architecture, and design of high-performance ASICs, owning complex functional areas.
• Define new verification methodologies to support advanced design architectures and develop reusable code for future projects.
• Lead design verification efforts by resolving block-level issues and participating in cluster and chip-level issue resolution.
• Architect, develop, and maintain cluster and top-level Design Verification (DV) environment infrastructure.
• Build DV environments from scratch for cluster and chip levels.
• Develop, implement, and enhance test plans and tests for cluster and chip verification using constraint-random and directed stimulus.
• Ensure comprehensive verification coverage through code and functional coverage implementation and review.
• Qualify RTL design by running Gate Level Simulations with timing annotation on netlists.
• Debug issues at ASIC, software, and systems levels, assisting in lab bring-up and post-silicon validation.

Qualifications:

• Bachelor's degree in Computer, Electrical, or Electronics Engineering with 7 years of relevant experience, or a Master's degree with 4 years of relevant experience focused on ASIC design and verification.
• Experience in Object-Oriented Programming (OOP) concepts, System Verilog, or UVM methodology.
• Experience leading verification teams or managing project assignments.
• Proficiency in scripting using Perl and/or Python.

Skills:

• Experience with forwarding logic, parsers, or P4.
• Familiarity with emulation platforms such as Veloce, Palladium, Zebu, or HAPS.
• Knowledge of formal verification tools (e.g., IEV or VC Formal).
• Domain knowledge in protocols such as PCIe, CXL, Ethernet, RDMA, DDR, or TCP.

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

Find the Right Semiconductor Partner

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

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