ASIC Design Verification Engineer I – Build & Verify Chips

AnySilicon; San Jose (CA); Presencial; USD 120.000 - 160.000; Jornada completa

Descripción de la vacante

Cisco's Silicon One team is seeking an ASIC Design Verification Engineer I for the United States. The role focuses on verifying ASIC designs and building robust DV environments to support Cisco's core networking platforms.

The ideal candidate brings SystemVerilog and UVM expertise, scripting skills in Perl or Python, and experience delivering constrained-random DV environments. You will collaborate across teams to ensure high-quality verification coverage.

Formación

• Bachelor's degree in ASIC Design, Design Verification or related field.
• Experience in ASIC Engineering or Verification is required.
• Proficient in SystemVerilog and UVM.
• Experience with coverage-driven verification and DV environments.
• Ability to build test benches from scratch and implement SystemVerilog constraints, classes and structures.

Responsabilidades

• Collaborate with verification engineers, designers, and cross-functional teams to ensure seamless integration of ASICs.
• Maintain and enhance existing design verification environments.
• Construct test benches including scoreboards, agents, sequencers, and monitors for new blocks.
• Write test plans, develop test cases, debug regression failures, and drive module verification closure.
• Ensure complete verification coverage through code and functional coverage implementation and review.

Conocimientos

SystemVerilog

UVM

Perl

Python

Constrained random

Test benches

Test plans

Communication

Educación

Bachelor's degree in ASIC Design or related field

Descripción del empleo

Cisco's Silicon One team is seeking an ASIC Design Verification Engineer I for the United States. The role focuses on verifying ASIC designs and building robust DV environments to support Cisco's core networking platforms.

The ideal candidate brings SystemVerilog and UVM expertise, scripting skills in Perl or Python, and experience delivering constrained-random DV environments. You will collaborate across teams to ensure high-quality verification coverage.