Senior ASIC Verification Architect

Cisco Systems, Inc; San Jose (CA); Presencial; USD 168.000 - 245.000; Jornada completa

Descripción de la vacante

Join Cisco Silicon One to help design verification for high-end switching ASICs. You will architect and maintain DV environments, develop models and test plans, and create testbenches.

Collaborate across teams to debug post-silicon issues and ensure full coverage. Ideal candidates bring SystemVerilog/UVM expertise, ASIC verification experience, and strong debugging skills, with Linux and programming in C/C++ or Python/Perl.

Formación

• Bachelor's degree or higher in electrical/computer science/computer engineering or related field.
• 7+ years of related experience or 4+ years with a Master’s or 1 year with a PhD in related field.
• Experience with SystemVerilog and UVM.
• Experience with ASIC design and verification processes, debugging, methodology, and tools.
• Experience in verifying blocks/clusters or full chip level for ASIC.

Responsabilidades

• Participate in the ASIC design verification for Cisco high-end switching products.
• Architect, develop, and maintain block, cluster, and top-level DV environment infrastructure.
• Develop simulation models, test plans, direct and random tests, code or functional coverage, multi-chip/system simulation, and performance analysis.
• Construct testbenches components like scoreboard, agents, sequencers, and monitors.
• Collaborate with designers, architects, and software teams to debug issues during post-silicon bring-up and integration.
• Ensure comprehensive verification coverage through code and functional coverage implementation and review.

Educación

Bachelor's degree in electrical/computer science/computer engineering/related degree

Master's degree in electrical/computer science/computer engineering/related degree

PhD in electrical/computer science/computer engineering/related degree

Herramientas

SystemVerilog

UVM

Ethernet protocols

PCIe/AXI protocols

Linux

C/C++

Python/Perl

Descripción del empleo

Join Cisco Silicon One to help design verification for high-end switching ASICs. You will architect and maintain DV environments, develop models and test plans, and create testbenches.

Collaborate across teams to debug post-silicon issues and ensure full coverage. Ideal candidates bring SystemVerilog/UVM expertise, ASIC verification experience, and strong debugging skills, with Linux and programming in C/C++ or Python/Perl.