Senior ASIC Timing Engineer – High-Speed SoCs

NVIDIA; Westford (MA); On-site; USD 168,000 - 311,000; Full time

Benefits offered by this job

Equity

Job summary

NVIDIA in Westford, MA is seeking Senior ASIC Timing Design Engineers to join the Networking Silicon team, delivering high-speed communication devices with lowest latency and highest throughput.

You will drive physical design and timing of DPUs/SoCs at block, chiplet, and full-chip levels, optimize constraints, and guide RTL-to-GDS2 flows, including ECO implementations and timing convergence. Equity and benefits are offered.

Qualifications

• BS in Electrical or Computer Engineering with 8 years experience or MS with 4+ years in Synthesis and Timing.
• Hands-on full-chip STA, timing constraints generation and management, and timing convergence.
• Experience fixing timing paths through ECOs including crosstalk and noise analysis.

Responsibilities

• Drive physical design and timing of high-frequency and low-power DPUs and SoCs at block, chiplet, and full chip levels.
• Analyze and optimize design constraints and synthesis parameters to meet performance, power and area targets.
• Support RTL-to-GDS2 flow including synthesis, ECOs, floorplanning, timing convergence and power management.

Skills

STA (Static Timing Analysis)

Timing Convergence

Synthesis & Timing

Python/Tcl/Make

EDA Tools expertise

RTLoFR/End-to-End flow

Education

BS in Electrical or Computer Engineering

MS in Electrical or Computer Engineering

Tools

Synopsys PrimeTime

Cadence Tempus

Job description

NVIDIA in Westford, MA is seeking Senior ASIC Timing Design Engineers to join the Networking Silicon team, delivering high-speed communication devices with lowest latency and highest throughput.

You will drive physical design and timing of DPUs/SoCs at block, chiplet, and full-chip levels, optimize constraints, and guide RTL-to-GDS2 flows, including ECO implementations and timing convergence. Equity and benefits are offered.