Senior ASIC Timing Engineer | Equity & Impact

Thomas To; Santa Clara (CA); On-site; USD 168,000 - 265,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking an ASIC Timing Engineer in Santa Clara to lead timing analysis and closure for GPUs, CPUs, LPUs, and SoCs. You’ll collaborate with RTL, DFX, and Clock teams to devise timing strategies, generate constraints, and drive convergence while applying ECOs.

The role requires hands-on STA experience and a track record of improving timing and power through design optimization. Join a team that values innovation and impact, with a base salary ranging from 136k to 264.5k USD depending on

Qualifications

• BS (or equivalent) in Electrical or Computer Engineering with 5 years’ experience or MS (or equivalent) with 3 years’ experience in Timing and STA.
• Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence.
• Expertise in analysis and fixing of timing paths through ECOs including crosstalk and noise analysis.
• Experience in physical design and optimization to improve timing and power.
• Expertise and in-depth knowledge of industry standard STA and timing convergence tools.
• Knowledge of deep sub‑micron process nodes and hands-on experience in modeling and converging timing in these nodes.

Responsibilities

• Lead timing analysis and closure for GPUs, CPUs, LPUs and SoCs at block, cluster, and full-chip levels.
• Collaborate with RTL, DFX, Clocks, and other teams to devise timing closure strategies and ECOs.
• Improve timing convergence flows in collaboration with methodology teams.

Skills

STA/Timing Analysis

Timing Closure

Crosstalk & Noise

Physical Design

EDA Tools

Education

BS in Electrical Engineering or Computer Engineering

MS in Electrical Engineering (preferred)

Tools

Synthesis

Placement

Routing

STA tools

Job description

NVIDIA is seeking an ASIC Timing Engineer in Santa Clara to lead timing analysis and closure for GPUs, CPUs, LPUs, and SoCs. You’ll collaborate with RTL, DFX, and Clock teams to devise timing strategies, generate constraints, and drive convergence while applying ECOs.

The role requires hands-on STA experience and a track record of improving timing and power through design optimization. Join a team that values innovation and impact, with a base salary ranging from 136k to 264.5k USD depending on