Senior ASIC Timing & Design Engineer (Equity)

NVIDIA Corporation; Westford, Northern (MA, KY); Hybrid; USD 168,000 - 311,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA Corporation in Massachusetts seeks a Senior ASIC Timing Engineer to join our Networking Silicon team in Westford. You will drive timing closure for high-frequency DPUs and SoCs from RTL to GDS2, analyzing constraints and optimizing performance, power, and area.

Ideal candidates hold a BS or MS in Electrical/Computer Engineering with 4–8+ years in synthesis, STA, ECOs, and physical design, and are proficient with PrimeTime or Tempus and scripting in Python/Tcl.

Qualifications

• BS in Electrical or Computer Engineering with 8 years' experience or MS with 4+ years in Synthesis and Timing.
• Hands-on STA across full-chip/sub-chip and timing convergence.
• Experience fixing timing paths with ECOs including crosstalk and noise analysis.
• Background in physical design: placement, routing, sizing, buffering, ECOs.
• Experience with industry tools such as PrimeTime or Tempus.
• Proficiency in Python and Tcl for automation.

Responsibilities

• Drive physical design and timing of high-frequency DPUs and SoCs at block, chiplet, or full-chip level.
• Analyze constraints and synthesis parameters to meet performance, power, and area targets.
• Lead frontend and backend from RTL to GDS2, including synthesis, equivalence checking, floorplanning, timing convergence, and ECO implementation.

Skills

Synthesis & Timing

STA (Static Timing Analysis)

Timing constraints

ECO timing closure

Python scripting

Education

BS in Electrical or Computer Engineering

MS in Electrical or Computer Engineering

Tools

Synopsys PrimeTime

Cadence Tempus

Job description

NVIDIA Corporation in Massachusetts seeks a Senior ASIC Timing Engineer to join our Networking Silicon team in Westford. You will drive timing closure for high-frequency DPUs and SoCs from RTL to GDS2, analyzing constraints and optimizing performance, power, and area.

Ideal candidates hold a BS or MS in Electrical/Computer Engineering with 4–8+ years in synthesis, STA, ECOs, and physical design, and are proficient with PrimeTime or Tempus and scripting in Python/Tcl.