Senior ASIC Timing & Physical Design Engineer (Equity)

NVIDIA Gruppe; Westford (MA); On-site; USD 180,000 - 300,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking a Senior ASIC Timing Design Engineer to join our Networking Silicon engineering team in Massachusetts. You will drive timing and physical design for high-frequency DPUs and SoCs, from block level to full-chip integration.

The role requires deep STA expertise, strong scripting for automation, and hands-on ECOs and timing convergence experience. We offer equity, comprehensive benefits, and the chance to work on cutting-edge AI hardware with global impact.

Qualifications

• BS/ MS in Electrical or Computer Engineering with 8 years (BS) or 4+ years (MS) in synthesis and timing.
• Hands-on experience in full-chip STA, timing constraints, and convergence.
• Expertise in ECOs, crosstalk and noise analysis.

Responsibilities

• Drive physical design and timing of high-frequency DPUs and SoCs at block, chiplet, and full-chip levels.
• Analyze and optimize constraints and synthesis parameters to meet performance, power, and area targets.
• Support frontend and backend flow from RTL to gds2, including ECO implementations.

Skills

Synthesis & Timing

STA timing analysis

Automation scripting

Education

BS in Electrical or Computer Engineering

MS in Electrical or Computer Engineering

Tools

Synopsys PrimeTime

Cadence Tempus

Job description

NVIDIA is seeking a Senior ASIC Timing Design Engineer to join our Networking Silicon engineering team in Massachusetts. You will drive timing and physical design for high-frequency DPUs and SoCs, from block level to full-chip integration.

The role requires deep STA expertise, strong scripting for automation, and hands-on ECOs and timing convergence experience. We offer equity, comprehensive benefits, and the chance to work on cutting-edge AI hardware with global impact.