Senior ASIC Physical Design & Netlisting Engineer

NVIDIA Corporation; Santa Clara (CA); On-site; USD 136,000 - 265,000; Full time

Job summary

NVIDIA Corporation seeks a Senior ASIC Physical Design Engineer, Netlisting, to drive high-frequency, low-power CPU/GPU/SoC design from block to full-chip level. You’ll handle netlist-related tasks, equivalence checking, and timing constraints while contributing to ECO implementation.

Applicants should have 5+ years (BS) or 3+ years (MS) in Electrical/Computer Engineering, with strong RTL/logic design, clock-domain crossing, and STA/EDA tool proficiency.

Qualifications

• BS or MS in Electrical or Computer Engineering with 3+ years (MS) or 5+ years (BS) experience.
• Expertise in logic equivalence checking from RTL to tapeout with common tools.
• Strong RTL/logic design and timing closure experience; SDA/EDA tool knowledge.

Responsibilities

• Drive physical design at block/cluster/full-chip level with focus on netlist aspects.
• Support timing convergence, constraints generation, ECOs, and timing closure.
• Work with team on clock-domain crossing checks and MTBF analysis.

Skills

Netlist equivalent checking

FV/IC design

RTL/logic design

Clock-domain crossing

Static Timing Analysis

Scripting (Python/TCL/Perl)

Education

Bachelor's or MS in Electrical/Computer Engineering

Tools

Industry standard EDA tools

Job description

NVIDIA Corporation seeks a Senior ASIC Physical Design Engineer, Netlisting, to drive high-frequency, low-power CPU/GPU/SoC design from block to full-chip level. You’ll handle netlist-related tasks, equivalence checking, and timing constraints while contributing to ECO implementation.

Applicants should have 5+ years (BS) or 3+ years (MS) in Electrical/Computer Engineering, with strong RTL/logic design, clock-domain crossing, and STA/EDA tool proficiency.