Senior ASIC Timing Architect | High‑Speed DPUs & SoCs

NVIDIA Corporation; Durham (NC); On-site; USD 168,000 - 264,500; Full time

Job summary

A leading technology company is seeking a Senior ASIC Timing Engineer in North Carolina to drive physical design and timing of high-frequency DPUs. Candidates should have a BS in Electrical or Computer Engineering with significant experience in Static Timing Analysis and relevant EDA tools. The company offers a competitive salary between $168,000 and $310,500 depending on experience along with potential equity. Join a diverse team dedicated to leading innovations in AI and computing.

Qualifications

• 8 years experience with BS or 4+ years with MS in Synthesis and Timing.
• Hands-on experience in full-chip and sub-chip STA.
• Background in logic synthesis/LEC.

Responsibilities

• Drive physical design and timing of high-frequency and low-power DPUs.
• Analyze and optimize design constraints for performance and power.
• Drive frontend and backend implementation from RTL to gds2.

Skills

Great teammate

Static Timing Analysis (STA)

Timing path analysis and fixing

Python

Tcl

Make

Education

BS in Electrical or Computer Engineering

MS in relevant field

Tools

Synopsys PrimeTime

Cadence Tempus

Job description

A leading technology company is seeking a Senior ASIC Timing Engineer in North Carolina to drive physical design and timing of high-frequency DPUs. Candidates should have a BS in Electrical or Computer Engineering with significant experience in Static Timing Analysis and relevant EDA tools. The company offers a competitive salary between $168,000 and $310,500 depending on experience along with potential equity. Join a diverse team dedicated to leading innovations in AI and computing.