Senior Physical Design & Timing Engineer AI/SoC Innovator

NVIDIA Corporation; Santa Clara (CA); Hybrid; USD 136,000 - 265,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA Corporation is seeking a Senior Physical Design and Timing Engineer to lead high-frequency and low-power design across CPUs, GPUs, LPUs and SoCs. The role emphasizes RTL-to-tapeout, floorplanning, and ECO troubleshooting with cross-functional collaboration across teams.

The position requires 5+ years (BS) or 3+ years (MS) in physical design, plus strong scripting and EDA proficiency. Equity benefits are included; applications accepted until Oct 3, 2026.

Qualifications

• BS in Electrical or Computer Engineering with 5+ years in physical design or MS with 3+ years.
• Hands-on experience from RTL to tapeout including synthesis, floorplanning, timing, signoff, ECOs.
• Proven improvements in power, performance, and area through design optimizations and timing closure.
• Experience in static timing analysis, timing constraints, and multi-mode/multi-corner timing closure.
• Proficiency with Python, Tcl, Perl, Make and scripting; knowledge of AI/ML/DL/LLMs.

Responsibilities

• Drive physical design and timing of high-frequency CPUs, GPUs, LPUs and SoCs at block, cluster, or full-chip level.
• Help drive frontend and backend implementation from RTL to GDS2, including synthesis, EC, floorplanning, timing constraints, timing/power convergence, ECOs.
• Work in a cross-functional environment interacting with multiple teams.

Skills

Python

Tcl

Perl

Make

AI/ML/DL/LLMs

Power/Perf/Area optimization

Education

BS in Electrical or Computer Engineering

MS in Electrical or Computer Engineering

Tools

EDA tools

Job description

NVIDIA Corporation is seeking a Senior Physical Design and Timing Engineer to lead high-frequency and low-power design across CPUs, GPUs, LPUs and SoCs. The role emphasizes RTL-to-tapeout, floorplanning, and ECO troubleshooting with cross-functional collaboration across teams.

The position requires 5+ years (BS) or 3+ years (MS) in physical design, plus strong scripting and EDA proficiency. Equity benefits are included; applications accepted until Oct 3, 2026.