ASIC RTL Design Engineer - High-Performance SoC

QUALCOMM, Inc.; San Diego (CA); On-site; USD 101,000 - 152,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking an ASIC Engineer to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP development for high-performance, low-power products.

You will collaborate with cross-functional teams and utilize RTL to GDS Flow and Virtuoso to execute architecture and design tasks across a block/SoC or IC package. Strong verbal and written communication are essential.

Qualifications

• Bachelor's degree in Science, Engineering, or related field.
• Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science (preferred).
• 6+ months of experience with architecture and design tools.
• 6+ months of experience with scripting tools and programming languages.
• 6+ months of experience with design verification methods.

Responsibilities

• Applies ASIC knowledge to assist in defining, modeling, designing, optimizing, verifying, validating, implementing, and documenting IP development for high-performance, low-power products.
• Assists in creating architectures, circuit specifications, logic designs, and system simulations.
• Collaborates to develop implementation strategies meeting system requirements and customer needs.
• Supports evaluation of design flow from high-level design to synthesis, place and route, timing and power use, and verification for custom design/layout.
• Writes technical documentation for EDA/IP/ASIC projects.

Skills

ASIC design

Digital/Analog design

Verilog/SystemVerilog

IP development

EDA tools

Scripting languages

Education

Bachelor's degree in EE/CS

Master's degree (preferred)

Tools

RTL to GDS Flow

Virtuoso

Job description

Qualcomm Technologies, Inc. is seeking an ASIC Engineer to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP development for high-performance, low-power products.

You will collaborate with cross-functional teams and utilize RTL to GDS Flow and Virtuoso to execute architecture and design tasks across a block/SoC or IC package. Strong verbal and written communication are essential.