High-Speed Digital ASIC Design Engineer (DDR/Interconnect)

Qualcomm Incorporated; San Diego (CA); On-site; USD 122,000 - 183,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking a motivated ASIC front-end design engineer to design, implement, and verify digital IPs for high-speed DDR and multi-die interfaces.

You will work with a world-class global team across architecture, verification, timing, and physical design to ensure reliable high-speed links from SoC to DRAM. Ideal candidates have hands-on experience with SystemVerilog, logic synthesis, lint checks, clock-domain crossing, low power sign-off, and gate-level debugging.

Qualifications

• Bachelors/Masters/PhD in Science or Engineering with relevant ASIC experience.
• Experience: 2+ years (Bachelors) or 1+ year (Masters) in ASIC design/verification.
• Industry experience with high-speed, low-power digital logic and front-end flows.

Responsibilities

• Design, develop RTL, and implement digital IPs for high-speed interfaces.
• Collaborate with systems, timing, verification and physical design teams for bring-up.

Skills

SystemVerilog

Logic Synthesis

Linting

Clock Domain Crossing

Low Power Design

Gate Level Simulation

DFT Flows

ASIC Front End

Education

Bachelor's degree in Science/Engineering

Master's degree in Science/Engineering

PhD in Science/Engineering

Tools

RTL Design Tools

Digital IP Design Tools

Job description

Qualcomm Technologies, Inc. is seeking a motivated ASIC front-end design engineer to design, implement, and verify digital IPs for high-speed DDR and multi-die interfaces.

You will work with a world-class global team across architecture, verification, timing, and physical design to ensure reliable high-speed links from SoC to DRAM. Ideal candidates have hands-on experience with SystemVerilog, logic synthesis, lint checks, clock-domain crossing, low power sign-off, and gate-level debugging.