Memory ASIC Engineer for High-Performance IP

QUALCOMM, Inc.; San Diego (CA); On-site; USD 122,000 - 183,000; Full time

Job summary

Qualcomm Technologies, Inc. seeks an ASIC Engineer to define, model, design (digital/analog), optimize, verify, and document IP/SoC development for high-performance, low-power products.

You will collaborate with cross-functional teams to meet system requirements and customer needs. The role requires strong experience in ASIC design/verification, scripting, and design tools; familiarity with RTL to GDS flow and Cadence Virtuoso is a plus.

Qualifications

• Bachelor's degree in Science, Engineering, or related field; 2+ years ASIC design/verification experience.
• Master's degree in Science, Engineering, or related field; 1+ year ASIC design/verification experience.
• PhD in Science, Engineering, or related field.
• Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science is preferred.

Responsibilities

• Defines, models, designs, optimizes, verifies, validates, implements, and documents IP/SoC development for high performance, low power products.
• Creates architectures, circuit specifications, and system simulations from requirements.
• Collaborates with software and hardware teams to meet system requirements and customer needs.
• Evaluates process flows from high-level design to synthesis, place-and-route, timing and power, and verification.

Skills

ASIC design

Verification

Scripting languages

System on Chip (SoC)

Education

Bachelor's degree in Engineering or related field

Master's degree in Science/Engineering

Tools

RTL to GDS Flow

Virtuoso

Job description

Qualcomm Technologies, Inc. seeks an ASIC Engineer to define, model, design (digital/analog), optimize, verify, and document IP/SoC development for high-performance, low-power products.

You will collaborate with cross-functional teams to meet system requirements and customer needs. The role requires strong experience in ASIC design/verification, scripting, and design tools; familiarity with RTL to GDS flow and Cadence Virtuoso is a plus.