ASIC/RTL Design Engineer for High-speed Interfaces

Nutanix; San Diego (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking highly skilled engineers to architect, verify, and implement digital designs for high-speed interface IPs such as SerDes and DDR. You will contribute to RTL development, micro-architecture, and PPA optimization across mixed-signal IP blocks.

You will collaborate with system architecture, analog teams, and DV/PD groups to ensure robust pre-/post-silicon bring-up and validation across Qualcomm’s product portfolio.

Qualifications

• Master’s degree in Electrical Engineering or Computer Engineering.
• 7+ years of experience in RTL and ASIC design.
• 5+ years in micro-architecture and digital design for mixed-signal IPs (SerDes, DDR, PLLs, DACs, ADCs).
• Proficiency with front-end ASIC design tools: VCS, Fusion Compiler, PrimeTime, Power Compiler, DFT Compiler, Spyglass.

Responsibilities

• Architect and define the digital design of high-speed interface IPs (SerDes, DDR, die-to-die).
• Develop micro-architecture and RTL for mixed-signal IP blocks.
• Enhance power, performance, and area (PPA) using advanced techniques.
• Use ASIC tools for lint, CDC, DFT, synthesis, FV, and STA.
• Design and analyze DFT logic, including ATPG coverage.
• Create design documentation and specs.
• Collaborate with DV and PD teams for test plans and timing closure.
• Support SoC integration and pre-/post-silicon bring-up.

Skills

RTL design

ASIC design

Micro-architecture

Digital design

SerDes

DDR PHY

VCS

Fusion Compiler

PrimeTime

Power Compiler

DFT Tools

Spyglass

Education

Master’s degree in Electrical Engineering

Master’s degree in Computer Engineering

Ph.D. in Electrical Engineering

Tools

VCS

Fusion Compiler

PrimeTime

Power Compiler

DFT Compiler

Spyglass

Job description

Company:

Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

The Mixed-Signal IP team at Qualcomm is seeking skilled micro architect and digital design engineers to contribute to the development of next-generation, high-performance, low-power interface IPs - including SerDes, DDR, and die-to-die interconnects - for integration across Qualcomm’s product portfolio, including mobile, compute, data center, and AI.

In this role, you will collaborate with a cross-functional team to architect, design, implement, and validate complex IP blocks. Your work will directly support multiple business units and require a strong grasp of the full ASIC design flow, from RTL through GDSII, along with an understanding of the challenges associated with advanced semiconductor technologies.

Responsibilities:

• Architect and define the digital design of high-speed interface IPs (e.g., SerDes, DDR, die-to-die) in close collaboration with system architecture and analog design teams
• Develop micro-architecture and implement RTL for complex mixed-signal IP blocks
• Apply advanced techniques in computer architecture, digital signal processing, and ASIC design to enhance power, performance, and area (PPA)
• Utilize industry-standard ASIC design tools for lint checking, clock domain crossing (CDC) analysis, design-for-test (DFT), synthesis, formal verification (FV), and static timing analysis (STA)
• Design and analyze DFT logic, including ATPG for stuck‑at fault (SAF) and transition delay fault (TDF) coverage
• Create comprehensive design documentation, including hardware specifications
• Collaborate with the design verification (DV) team to define test plan, verify the design, and fix bugs
• Work with the physical design (PD) team to support floorplanning, placement, and timing closure of IPs
• Support SoC integration and debug, including pre‑silicon simulation and post‑silicon bring‑up

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.ORMaster's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.ORPhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Required for this Role:

• Master’s degree in Electrical Engineering, Computer Engineering, or a related field
• 7+ years of experience in RTL and ASIC design
• 5+ years of hands‑on experience in micro‑architecture and digital design for mixed‑signal IPs such as SerDes (PCIe, USB, UFS, MIPI), DDR PHY, PLLs, DACs, ADCs, and sensors
• Proficiency with industry‑standard front‑end ASIC design tools including VCS, Fusion Compiler, PrimeTime, Power Compiler (PTPX), DFT Compiler, Spyglass, and others

Preferred Qualifications

• Ph.D. in Electrical Engineering with 5+ years of industry experience in high‑speed digital circuit design
• Strong background in low‑power digital design techniques
• Expertise in computer architecture, digital signal processing, and algorithm development
• Experience developing automation scripts and design productivity tools using Python or Perl

Equal Opportunity & Diversity Statement:

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e‑mail disability‑[e-mail] or call Qualcomm's toll‑free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

Pay range and Other Compensation & Benefits:

$140,000.00 - $210,000.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales‑incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.