Senior ASIC RTL & Mixed-Signal IP Architect

QUALCOMM, Inc.; San Diego (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking highly skilled engineers to architect, verify, and implement digital designs for high-speed interface IPs such as SerDes and DDR. You will contribute to RTL development, micro-architecture, and PPA optimization across mixed-signal IP blocks.

You will collaborate with system architecture, analog teams, and DV/PD groups to ensure robust pre-/post-silicon bring-up and validation across Qualcomm’s product portfolio.

Qualifications

• Master’s degree in Electrical Engineering or Computer Engineering.
• 7+ years of experience in RTL and ASIC design.
• 5+ years in micro-architecture and digital design for mixed-signal IPs (SerDes, DDR, PLLs, DACs, ADCs).
• Proficiency with front-end ASIC design tools: VCS, Fusion Compiler, PrimeTime, Power Compiler, DFT Compiler, Spyglass.

Responsibilities

• Architect and define the digital design of high-speed interface IPs (SerDes, DDR, die-to-die).
• Develop micro-architecture and RTL for mixed-signal IP blocks.
• Enhance power, performance, and area (PPA) using advanced techniques.
• Use ASIC tools for lint, CDC, DFT, synthesis, FV, and STA.
• Design and analyze DFT logic, including ATPG coverage.
• Create design documentation and specs.
• Collaborate with DV and PD teams for test plans and timing closure.
• Support SoC integration and pre-/post-silicon bring-up.

Skills

RTL design

ASIC design

Micro-architecture

Digital design

SerDes

DDR PHY

VCS

Fusion Compiler

PrimeTime

Power Compiler

DFT Tools

Spyglass

Education

Master’s degree in Electrical Engineering

Master’s degree in Computer Engineering

Ph.D. in Electrical Engineering

Tools

VCS

Fusion Compiler

PrimeTime

Power Compiler

DFT Compiler

Spyglass

Job description

Qualcomm Technologies, Inc. is seeking highly skilled engineers to architect, verify, and implement digital designs for high-speed interface IPs such as SerDes and DDR. You will contribute to RTL development, micro-architecture, and PPA optimization across mixed-signal IP blocks.

You will collaborate with system architecture, analog teams, and DV/PD groups to ensure robust pre-/post-silicon bring-up and validation across Qualcomm’s product portfolio.