High-Speed ASIC Front-End Design Engineer (DDR)

QUALCOMM, Inc.; San Diego (CA); On-site; USD 122,000 - 183,000; Full time

Job summary

Qualcomm Technologies, Inc. seeks an ASIC front end design engineer for its high-speed parallel interfaces team.

You will design RTL and implement digital IPs for SoC-to-DRAM interfaces and multi-die links, collaborating with architecture, verification, timing, and physical design engineers to deliver high-performance, reliable interfaces. The role requires SystemVerilog expertise, gate‑level simulation, low‑power techniques, and experience with front end tool flows and silicon bring‑up in a

Qualifications

• Bachelor’s degree in Science, Engineering, or related field.
• Minimum 4 years ASIC design, verification, or related work experience.
• Hands-on experience with SystemVerilog and ASIC front end tool flows.
• Experience with high-speed parallel interfaces and low-power design.
• Design for test flows and silicon bring-up experience.

Responsibilities

• Design RTL and implement digital IPs for SoC interfaces.
• Collaborate with architecture, timing, verification and physical design teams.
• Develop and debug gate-level simulations; optimize power and timing.

Skills

SystemVerilog

RTL design

ASIC front end design

Low power design

Clock domain crossing

Education

Bachelor’s Degree in Science, Engineering, or related field

Master’s degree in Science, Engineering, or related field

PhD in Science, Engineering, or related field

Job description

Qualcomm Technologies, Inc. seeks an ASIC front end design engineer for its high-speed parallel interfaces team.

You will design RTL and implement digital IPs for SoC-to-DRAM interfaces and multi-die links, collaborating with architecture, verification, timing, and physical design engineers to deliver high-performance, reliable interfaces. The role requires SystemVerilog expertise, gate‑level simulation, low‑power techniques, and experience with front end tool flows and silicon bring‑up in a