Senior ASIC RTL Engineer - DFT & Frontend-Backend Lead

Cisco; Austin (TX); Presencial; USD 150.000 - 260.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Medical, dental, vision

401(k) with matching

Paid time off

Descripción de la vacante

Cisco Systems, Inc is seeking a senior hardware engineer focusing on DFT RTL for Silicon One. You will collaborate with front-end RTL and backend physical design teams to drive robust, testable silicon architectures that meet Cisco’s high-performance standards.

Responsibilities include driving Verilog/SystemVerilog development, leveraging DFT/MBIST techniques, and ensuring memory and AMBA/JTAG interface compatibility across advanced networking silicon.

Formación

• Requires a Bachelor's or Master's in Electrical or Computer Engineering with at least 8 years of experience.
• Experience with Verilog/SystemVerilog coding.
• Experience with front-end tools: Verilog simulators, linting, CDC checkers, synthesis, formal verification.
• Familiarity with AMBA, JTAG, and memory interfaces.

Responsabilidades

• Drive high-quality design-for-test RTL to ensure robust silicon.
• Collaborate with Front-end RTL and backend physical design teams to understand chip architecture.
• Deliver silicon solutions that meet performance and innovation standards.

Conocimientos

Verilog/SystemVerilog

Front-end tools

AMBA/JTAG interfaces

Memory interfaces

Power optimization

DFT/MBIST

Post-silicon debug

Educación

Bachelor's or Master’s in Electrical or Computer Engineering

Herramientas

Verilog simulators

Linting

CDC checkers

Synthesis

Formal verification

AMBA protocols

JTAG

Memories interfaces

Descripción del empleo

Cisco Systems, Inc is seeking a senior hardware engineer focusing on DFT RTL for Silicon One. You will collaborate with front-end RTL and backend physical design teams to drive robust, testable silicon architectures that meet Cisco’s high-performance standards.

Responsibilities include driving Verilog/SystemVerilog development, leveraging DFT/MBIST techniques, and ensuring memory and AMBA/JTAG interface compatibility across advanced networking silicon.