Senior ASIC Physical Design Engineer – Space-Grade Silicon

Spacex; Palo Alto (CA); On-site; USD 175,000 - 280,000; Full time

Job summary

SpaceX is seeking a Sr. SOC/ASIC Physical Design Engineer to advance next-generation silicon for Starlink satellites and ground systems. You’ll work with cross-disciplinary teams to push timing, power, and area targets across the full flow from RTL to GDSII.

The role demands deep experience with ASIC/SOC physical design, signoff flows, and strong scripting ability to automate processes. On-site at SpaceX compensation includes a strong package and long-term incentives.

Qualifications

• BS degree in a relevant engineering field.
• 5+ years of ASIC/physical design flow experience.
• Proficiency with RTL2GDSII signoff flows and EDA tools.

Responsibilities

• Perform partition synthesis and physical implementation steps.
• Develop/improve physical design methodologies and scripts.
• Collaborate with ASIC team to drive timing, power and area targets.
• Resolve design/timing/congestion issues and drive execution.
• Run signoff checks in STA, noise, physical verification and electromigration.

Skills

RTL2GDSII

EDA tools

FinFET/CMOS physics

CMOS digital design

CMOS power dissipation

CMOS analog design

DFT/MBIST/LBIST

Scripting (Python, TCL, Perl, Bash)

Self-driven

Education

Bachelor’s degree in electrical engineering, computer engineering or computer science

Tools

EDA tools

Job description

SpaceX is seeking a Sr. SOC/ASIC Physical Design Engineer to advance next-generation silicon for Starlink satellites and ground systems. You’ll work with cross-disciplinary teams to push timing, power, and area targets across the full flow from RTL to GDSII.

The role demands deep experience with ASIC/SOC physical design, signoff flows, and strong scripting ability to automate processes. On-site at SpaceX compensation includes a strong package and long-term incentives.