Senior ASIC & RTL Design Engineer - Analog/Mixed-Signal

TPI Global Solutions; San Jose (CA); On-site; USD 130,000 - 195,000; Full time

Job summary

TPI Global Solutions seeks an experienced ASIC/RTL Design Engineer with strong RTL coding and hands-on analog design experience. You will develop RTL blocks in Verilog/SystemVerilog, simulate with VCS, and model analog/mixed-signal behavior, collaborating to deliver integrated ASIC solutions.

Responsibilities include design, debugging, testbench development, and optimization across digital and analog teams, using VCS, LTspice, and HSPICE.

Qualifications

• Experience in ASIC design and RTL coding.
• Proficiency in Verilog and/or SystemVerilog.
• Hands-on analog design or AMS modeling experience.
• Experience with Synopsys VCS, LTspice, and HSPICE.
• Strong digital logic knowledge and ASIC design methodologies.
• Ability to debug RTL and analog simulation issues.

Responsibilities

• Develop, implement, and maintain RTL code for ASIC and digital design blocks.
• Perform RTL design, simulation, and debugging for correctness and quality.
• Contribute to analog design and modeling activities and AMS interfaces.
• Use Synopsys VCS for RTL simulation and verification.
• Run analog simulations with LTspice and HSPICE.
• Collaborate with analog/digital teams to integrate RTL with mixed-signal blocks.
• Analyze results, identify issues, and troubleshoot at circuit level.
• Develop testbenches, models, and design documentation.
• Support verification, timing analysis, and optimization throughout ASIC development.

Skills

RTL coding

Verilog/SystemVerilog

Digital design

Analog modeling

Debugging RTL

Collaboration

Tools

Synopsys VCS

LTspice

HSPICE

Job description

TPI Global Solutions seeks an experienced ASIC/RTL Design Engineer with strong RTL coding and hands-on analog design experience. You will develop RTL blocks in Verilog/SystemVerilog, simulate with VCS, and model analog/mixed-signal behavior, collaborating to deliver integrated ASIC solutions.

Responsibilities include design, debugging, testbench development, and optimization across digital and analog teams, using VCS, LTspice, and HSPICE.