Senior RTL Design Engineer – ASICs & PPA (Contract)

OHO Group (Lithuania); Austin (TX); On-site; USD 83,000 - 152,000; Full time

Job summary

OHO Group (Lithuania) is seeking multiple experienced Senior RTL Design Engineers to support the development of custom ASICs on ambitious projects. You will own complex design challenges across the RTL to GDSII lifecycle and collaborate with verification and physical design teams.

Candidates should bring 5+ years in RTL design, proficiency with Verilog/SystemVerilog, and hands-on experience with PPA and low power techniques. Strong collaboration and problem-solving skills are essential.

Qualifications

• 5+ years of RTL design experience in ASIC/SoC projects.
• Strong background in Verilog/SystemVerilog for large-scale designs.
• Hands-on PPA and low-power design experience.
• Collaborative, cross-functional teammate across design and verification.

Responsibilities

• Develop and optimize RTL for complex ASIC blocks.
• Lead design reviews and collaborate with verification and physical design teams.
• Support timing, power, area goals and debug complex issues.

Skills

RTL Design

ASIC design

Verilog

SystemVerilog

PPA

Low Power Design

Architecture

Verifications

Collaboration

Tools

Cadence

Synopsys

PrimeTime

Job description

OHO Group (Lithuania) is seeking multiple experienced Senior RTL Design Engineers to support the development of custom ASICs on ambitious projects. You will own complex design challenges across the RTL to GDSII lifecycle and collaborate with verification and physical design teams.

Candidates should bring 5+ years in RTL design, proficiency with Verilog/SystemVerilog, and hands-on experience with PPA and low power techniques. Strong collaboration and problem-solving skills are essential.