Senior ASIC RTL Design Engineer with Silicon Bring-Up

Insight Global; United States; On-site; USD 140,000 - 210,000; Full time

Job summary

Insight Globals is seeking an RTL Designer to own key sub-blocks within large, advanced-node mixed-signal ASICs supporting next-generation SoC and memory test products. This engineer will partner with chip architects, verification engineers, physical design, software, and silicon bring-up teams throughout the ASIC development lifecycle.

The role includes defining requirements, creating microarchitecture, RTL development, verification support, and post-silicon debug.

Qualifications

• 20+ years of ASIC/SoC RTL design experience.
• Proven ownership of ASIC blocks from requirements through silicon bring-up.
• Experience translating architecture requirements into specifications, microarchitecture, and RTL.
• Experience supporting designs through verification, implementation, and silicon validation.
• Experience designing complex digital logic including FSMs, FIFOs, datapaths, and control logic.

Responsibilities

• Own key sub-blocks within large, advanced-node mixed-signal ASICs.
• Collaborate with chip architects, verification engineers, physical design, software, and silicon bring-up teams.
• Define requirements, create microarchitecture, RTL development, verification support, and post-silicon debug.
• Take ownership of a block from specification through silicon validation.

Skills

ASIC/SoC RTL design

Block ownership

Architecture to RTL

Verification support

Digital logic design (FSMs, FIFOs)

Tools

PCIe Gen5

LPDDR5

NVMe

UFS 4.1

Job description

Insight Globals is seeking an RTL Designer to own key sub-blocks within large, advanced-node mixed-signal ASICs supporting next-generation SoC and memory test products. This engineer will partner with chip architects, verification engineers, physical design, software, and silicon bring-up teams throughout the ASIC development lifecycle.

The role includes defining requirements, creating microarchitecture, RTL development, verification support, and post-silicon debug.