RTL design

Mirafra Technologies; San Francisco (CA); On-site; USD 170,000 - 230,000; Full time

Job summary

Mirafra Technologies is seeking a senior RTL design lead to develop high-performance ASIC/SoC blocks. You will own block-level design from spec to tapeout, driving RTL coding, verification readiness, and integration with architecture and physical design teams.

The role emphasizes PPA optimization, low-power techniques, and cross-functional collaboration, with mentoring duties for junior engineers and strong leadership expectations.

Qualifications

• 7+ years of hands-on ASIC/SoC RTL design.
• Strong expertise in Verilog/SystemVerilog and digital design fundamentals.
• Proven experience in micro-architecture development and block ownership.
• Strong knowledge of AMBA AXI/AHB/APB, clock/reset design, and SoC integration.
• Experience with Lint, CDC/RDC, synthesis, STA, and timing closure.
• Understanding of low-power design, UPF/CPF, clock gating, and power domains.
• Experience with Synopsys, Cadence, or Siemens EDA tools.
• Scripting experience in Python, Tcl, Perl, or Shell.
• Strong debugging, communication, technical leadership, and cross-functional collaboration skills.

Responsibilities

• Lead RTL design and micro-architecture development for ASIC/SoC blocks.
• Own block-level design from specification through RTL signoff and tapeout.
• Design data paths, control logic, FSMs and pipelines.
• Drive PPA optimization and design trade-offs.
• Lead RTL lint, CDC/RDC, synthesis, STA, low-power and connectivity checks.
• Collaborate with Architecture, Verification, Physical Design, and Firmware teams.
• Mentor engineers and provide technical leadership and ownership.

Skills

ASIC/SoC RTL design

Verilog/SystemVerilog

Micro-architecture development

AMBA AXI/AHB/APB

Lint/CDC/RDC/synthesis/STA

Low-power design (UPF/CPF)

EDA tool proficiency (Synopsys/Cadence

Scripting (Python/Tcl/Perl/Shell)

Debugging and leadership

Tools

Synopsys

Cadence

Siemens EDA

Job description

• Lead RTL design and micro-architecture development for complex ASIC/SoC blocks and subsystems.
• Translate architecture and system requirements into high-quality, synthesizable Verilog/SystemVerilog RTL.
• Own block-level design from specification through RTL signoff and tapeout.
• Design data paths, control logic, FSMs, pipelines, clock/reset architecture, and high-performance digital logic.
• Drive PPA (Power, Performance, Area) optimization and design trade-offs.
• Lead RTL Lint, CDC/RDC, synthesis, STA, low-power and connectivity checks.
• Work closely with Architecture, Design Verification, Physical Design, DFT, Firmware, and Validation teams.
• Debug issues across simulation, synthesis, implementation, and post-silicon bring-up.
• Participate in design reviews and establish RTL coding/design best practices.
• Mentor junior and senior engineers and provide technical leadership and design ownership.

Required Skills:

• 7+ years of hands-on ASIC/SoC RTL design experience.
• Strong expertise in Verilog/SystemVerilog and digital design fundamentals.
• Proven experience in micro-architecture development and block ownership.
• Strong knowledge of AMBA AXI/AHB/APB, clock/reset design, and SoC integration.
• Experience with Lint, CDC/RDC, synthesis, STA, and timing closure.
• Understanding of low-power design, UPF/CPF, clock gating, and power domains.
• Experience with Synopsys, Cadence, or Siemens EDA tools.
• Scripting experience in Python, Tcl, Perl, or Shell.
• Strong debugging, communication, technical leadership, and cross-functional collaboration skills.