Senior ASIC Physical Design Engineer, Full-Chip

Google Inc.; Mountain View (CA); On-site; USD 138,000 - 197,000; Full time

Job summary

Google Inc. is seeking a Mid-level Physical Design Engineer in Mountain View, CA to drive ASIC RTL2GDS implementation with focus on high performance, power, and area. You will work with cross-functional teams to deliver top-tier silicon features and optimizations for Google's products.

The role requires a Bachelor's in Electrical Engineering, 4 years in physical design, and hands-on experience with synthesis/PnR flows. Strong Verilog/SystemVerilog and scripting skills are highly valued.

Qualifications

• Bachelor's degree in Electrical Engineering or equivalent.
• 4 years of experience in physical design.
• Experience with synthesis/PnR tools (Genus, Innovus, DC, ICC) and sign-off convergence.

Responsibilities

• Develop ASIC RTL2GDS implementation for high-Performance, Power, Area (PPA).
• Define schemes to improve performance and power.
• Collaborate with cross-functional teams to deliver high-quality results.

Skills

Physical design

Synthesis & PnR

Sign-off convergence

Verilog/SystemVerilog

Tcl/Perl scripting

Education

Bachelor's degree in Electrical Engineering

Tools

Genus

Innovus

DC

ICC

Job description

Google Inc. is seeking a Mid-level Physical Design Engineer in Mountain View, CA to drive ASIC RTL2GDS implementation with focus on high performance, power, and area. You will work with cross-functional teams to deliver top-tier silicon features and optimizations for Google's products.

The role requires a Bachelor's in Electrical Engineering, 4 years in physical design, and hands-on experience with synthesis/PnR flows. Strong Verilog/SystemVerilog and scripting skills are highly valued.