Senior ASIC Physical Design Engineer — RTL2GDS Lead + Equity

Google; Mountain View (CA); On-site; USD 163,000 - 236,000; Full time

Job summary

Google is seeking a senior Electrical Engineer to lead physical design for custom ASICs powering Google products. You will drive RTL2GDS implementation, manage full-chip physical work, and optimize for power, performance, and area.

A Bachelor's degree in Electrical Engineering and about 8 years of physical design exposure are required, with hands-on experience in synthesis/PnR tools and STA sign-off. This role includes a competitive package with equity and benefits, and a strong emphasis on

Qualifications

• Bachelor's degree in Electrical Engineering or equivalent practical experience.
• 8 years of physical design experience.
• Experience with one or more synthesis/PnR tools: Genus, Innovus, DC, ICC.
• Experience in STA and sign-off convergence/optimizations.

Responsibilities

• Develop RTL2GDS implementation for high Power, Performance, and Area (PPA) designs.
• Manage full-chip level physical implementation.
• Define and implement innovative schemes to improve Performance and Power.
• Work with cross functional teams to deliver best Quality of results.

Skills

Synthesis & PnR

STA sign-off

Cross-functional

Tcl/Perl scripting

Education

Bachelor's degree in EE

Tools

Genus

Innovus

DC

ICC

Job description

Google is seeking a senior Electrical Engineer to lead physical design for custom ASICs powering Google products. You will drive RTL2GDS implementation, manage full-chip physical work, and optimize for power, performance, and area.

A Bachelor's degree in Electrical Engineering and about 8 years of physical design exposure are required, with hands-on experience in synthesis/PnR tools and STA sign-off. This role includes a competitive package with equity and benefits, and a strong emphasis on