Senior ASIC Physical Design Engineer - RTL to GDSII Expert

Cisco; San Jose (CA); On-site; USD 168,000 - 245,000; Full time

Job summary

Cisco's Common Hardware Group seeks a Physical Design Engineer to drive RTL-to-GDSII implementation across advanced nodes, delivering high-performance networking chips. You will optimize floor planning, timing, and power distribution while collaborating with RTL, DFT, and EDA teams.

The role emphasizes hands-on physical design, timing closure, and tool-driven flow improvements across multi-node projects, with opportunities to shape industry-leading silicon.

Qualifications

• Bachelors degree in Electrical Engineering with 5+ years of related experience, or Masters with 2+ years, or PhD with 0+ years.
• Hands-on ASIC physical design and implementation experience.
• Experience with hierarchical floorplanning, clock/power distribution, global signal/I/O planning, and convergence.
• Experience with designs >100M gates in advanced nodes (16nm–2nm).

Responsibilities

• Own RTL-to-GDSII implementation for advanced nodes (sub-16nm to 2nm).
• Define hierarchical floor planning, place & route, clock and power distribution, and timing convergence strategies.
• Perform STA, setup reviews, and sign-offs for multi-mode/multi-corner designs; develop automated scripts in STA tools.
• Implement and manage timing ECO strategies using Prime Closure/PrimeTime.
• Analyze quality and efficiency gaps; recommend tool/flow/methodology improvements.
• Collaborate with RTL, DFT, EDA vendors, and tool owners to drive design efficiency.
• Evaluate new timing methodologies; provide debugging solutions.
• Drive methodology alignment across projects.

Skills

asic physical design

floorplanning

timing convergence

static timing analysis

rtl-to-gdsii

power integrity

scripting

place & route

tool fluency

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

PhD in Electrical Engineering

Tools

Cadence Innovus

Synopsys FC

Cadence Genus

Synopsys Formality

PrimeTime-DMSA

Cadence LEC

Mentor Calibre

PrimeTime

Voltus/Redhawk

Job description

Cisco's Common Hardware Group seeks a Physical Design Engineer to drive RTL-to-GDSII implementation across advanced nodes, delivering high-performance networking chips. You will optimize floor planning, timing, and power distribution while collaborating with RTL, DFT, and EDA teams.

The role emphasizes hands-on physical design, timing closure, and tool-driven flow improvements across multi-node projects, with opportunities to shape industry-leading silicon.