Senior ASIC Physical Design Engineer – RTL2GDS, Power

Google LLC; Mountain View (CA); On-site; USD 163,000 - 236,000; Full time

Benefits offered by this job

Equity

Bonus target

Benefits

Job summary

Google LLC in Mountain View, CA, is seeking a Senior Physical Design Engineer for FullChip/ASIC Implementation. You will lead RTL2GDS flows, target high performance, and collaborate across teams to deliver cutting-edge silicon solutions.

The role requires a Bachelor's degree in Electrical Engineering or equivalent and 8+ years of physical design experience, with strong experience in Genus, Innovus, DC, or ICC and scripting in Tcl/Perl is a plus.

Qualifications

• Bachelor's degree in Electrical Engineering or equivalent practical experience.
• 8 years of physical design experience.
• Experience in synthesis/PnR tools (Genus, Innovus, DC, ICC).
• Experience in high-performance synthesis, PnR, sign-off convergence.

Responsibilities

• Develop all aspects of ASIC RTL2GDS implementation for high PPA designs.
• Define and implement schemes to improve Performance and Power.
• Work with cross-functional teams to deliver high-quality results.

Skills

Physical design

8 years experience

Education

Bachelor's degree in Electrical Engineering or equivalent

Tools

Genus

Innovus

DC

ICC

Job description

Google LLC in Mountain View, CA, is seeking a Senior Physical Design Engineer for FullChip/ASIC Implementation. You will lead RTL2GDS flows, target high performance, and collaborate across teams to deliver cutting-edge silicon solutions.

The role requires a Bachelor's degree in Electrical Engineering or equivalent and 8+ years of physical design experience, with strong experience in Genus, Innovus, DC, or ICC and scripting in Tcl/Perl is a plus.